1. Field of the Invention
The present invention relates to a COC (Chip On Chip) device, which configures one system in a manner that a semiconductor chip is stacked with another semiconductor chip having a function different from the preceding semiconductor chip, and a SiP (System in Package) device, for example, MCM (Multi Chip Module) device, which configures one system in a manner that one package includes a plurality of chips.
2. Description of the Related Art
In recent years, a so-called SOC (System On Chip) technology has been researched and developed. More specifically, functions realized by CPU and IP (Intellectual Property), memories (e.g., SRAM, DRAM and flash memory) and analog LSI (e.g., RF circuit) are embedded in one chip so that one system can be formed in one chip. One system is formed in one chip, and thereby, there is no need of mutually connecting a plurality of chips by external interconnection lines (metal wires); therefore, it is possible to realize high performance system and system miniaturization.
However, in order to realize an LSI (hereinafter, referred to as SOC) embedding a plurality of functions in one chip, there are various difficult problems to solve.
For example, a memory embedded logic LSI and an analog embedded logic LSI have been known as a typical SOC. In the above memory embedded logic LSI, a process peculiar to memory (e.g., in the case of DRAM, trench/stack capacitor manufacturing process) must be added to a logic process. Moreover, in the above analog embedded logic LSI, a process peculiar to analog circuit (e.g., bipolar transistor manufacturing process) must be added to a logic process.
For this reason, in the above-mentioned SOC, the manufacturing process (hereinafter, referred to as embedded process) is very complicate and becomes long. As a result, there remain problems such as a reduction of yield and an increase of the manufacture cost.
Further, naturally, the above-mentioned SOC is formed in a manner that a plurality of functions (chips), which has been formed by mutually different manufacturing process, is incorporated into one chip. For this reason, it is a significant matter to optimize an embedded process when forming one chip. However, in this case, since different plural manufacturing processes are incorporated into one embedded process in common, of course, compromise must be made in device performance or integration in the case of incorporating different processes in common.
For example, in a DRAM embedded-logic LSI, a logic process is used as base, and a process peculiar to DRAM is added to the logic process. In this case, the logic process includes a Salicide (Self-Align silicide) process for reducing each resistance of gate, source and drain of a MOS transistor. On the other hand, a DRAM process includes a SAC (Self-Align Contact) for achieving a high integration of memory-cell.
However, according to current process technology, if the silicide process and the SAC process are incorporated into one manufacturing process (embedded process), a number of a process steps are sharply increased and a cost of a chip is upped. For decrease of the chip cost, it doesn't become easy to employ both of the above silicide and SAC processes, namely, any one of the above silicide and SAC processes must be abandoned.
Temporarily, in the case where logic performance is preferentially considered, the Salicide process is employed; on the other hand, the SAC process is not employed. As a result, a memory cell side becomes large; for this reason, it is disadvantage to achieve high integration of memory cell. Conversely, in the case where the above high integration of memory cell is preferentially considered, the SAC process is employed; on the other hand, the Salicide process is not employed. As a result, the logic performance is reduced.